1. Field of the Invention
The present invention generally relates to semiconductor memories, and more particularly, the present invention relates to non-volatile memory devices and to methods of erasing non-volatile memory devices.
A claim of priority under 35 U.S.C. §119 is made to Korean patent application nos. 10-2006-0118537 and 10-2006-0118358, both filed Nov. 28, 2007, the entireties of which are incorporated herein by reference.
2. Description of the Related Art
An example of the cell string structure of a conventional NAND flash memory device is illustrated in FIG. 1.
Referring to FIG. 1, a first cell string 10 includes flash memory cells MC<0:31> gated to respective word lines WL<0:31>. The flash memory cells MC<0:31> are connected in series between a ground select transistor GST and a string select transistor SST. The ground select transistor GST is gated to a ground select line GSL, and the string select transistor SST is gated to a string select line SSL. Also, as shown, the first cell string 10 is connected between a bit line 1HB_BL and a common select line CSL.
A second cell string 20 is similarly configured and includes flash memory cells MC<0′:31′> gated to the respective word lines WL<0:31>. The flash memory cells MC<0′:31′> are connected in series between a ground select transistor GST′ and a string select transistor SST′. The ground select transistor GST′ is gated to the ground select line GSL, and the string select transistor SST′ is gated to the string select line SSL. The second cell string 20 is connected between a bit line PGM_BL and the common select line CSL.
Each flash memory cell MC may be single-bit memory element storing one-bit of data, or multi-bit memory element storing two or more bits of data. As is well-understood by those skilled in the art, data is stored in each cell by altering the threshold voltage of the cell. For example, each cell is programmed into one of two threshold distributions in the case of single-bit cells, and each cell is programmed into one of four threshold distributions in the case of two-bit cells.
FIG. 2 is a diagram for describing an example of the programming sequence utilized to program a multi-bit cell (MBC). In particular, the illustrated example is for programming of a two-bit flash memory cell. In the figure, the bell-curves denote threshold voltages distributions of different programmed states of the multi-bit flash memory cells, and VR1˜VR3 denote read word line voltages which are utilized in a read operation of the multi-bit flash memory cells.
Generally, in NAND-type flash memory systems, memory cells are placed in an “erased state” prior to programming. In FIG. 2, the erased state is the lowest threshold voltage distribution and is assigned the two-bit data value of “11”. The three higher threshold voltage distributions of the figure correspond to “programmed states” and are sequentially assigned two-bit data values of “10”, “00” and “01”. A sequence of three programming operations are selectively executed in order to program a cell from the erased state “11” to any one of the programmed states “10”, “00” or “01”. That is, a least-significant-bit (LSB) program (Program 1) operation is performed on cells where the LSB of the two-bit data value is to be changed from “1” to “0”. A first most-significant-bit (MSB) program (Program 2) operation is performed on cells where the LSB has been changed in Program 1 and where the MSB of the two-bit data value is to be changed from “1” to “0”. A second MSB program (Program 3) is performed on cells where only the MSB is to be changed from “1” to “0”.
Referring to the circuit diagram of FIGS. 3 and 4, the programming of the memory cell “B” (FIG. 4) illustrated therein will now be explained. As shown, the memory cell B (i.e., the program cell B) is coupled to word line WL28 and program bit line PGM_BL. The NAND string having the program bit line PGM_BL is referred to herein as a program string. FIG. 4 also illustrates a memory cell “A” connected to the word line WL28 and bit line IHB_BL. This memory cell is not to be programmed and is referred to as an inhibit cell A contained within an inhibit string.
Conventionally, programming operations are executed in sequence from word line WL0 to word line WL31. Referring to FIG. 3, after an initial set-up period (t1˜t3) in which the string select line SSL is brought to voltage (Vsel) between VCC and a threshold voltage Vth, a pass voltage Vpass (e.g., about 8V) is applied to each of the word lines WL<0:31>. Then, at time t3, the voltage of the word line WL28 rises to a program voltage Vpgm (e.g., about 18V). During this time, programming of the threshold voltage of memory cell B occurs. Then, at time t5, the voltage of the word line WL28 begins to drop, and at time t6, all the word line WL voltages are dropped to 0V.
Upon programming of the program cell B, a voltage of 0V is applied to the bulk thereof through the 0V applied to the bit line PGM_BL, and the program voltage Vpgm is applied to the word line WL28. In this state, F-N tunneling is induced in the program cell B, thus increasing the threshold voltage thereof as is well known in the art. In the meantime, F-N tunneling within the inhibit cell A does not occur due to self-boosting of the bulk thereof resulting from the application of the reference voltage VCC to the inhibit bit line 1HB_BL.
In the example of FIG. 4, the memory cells in the inhibit string are in the erased state (“11”). The resultant low threshold of the cells creates a high boosting efficiency, the preventing F-N tunneling in these cells. In contrast, FIG. 5 illustrates an example in which a memory cell D of a program string is to be programmed, and a memory cell C of an inhibit string is to be programmed inhibited. The memory cells connected to the word lines WL<0:27> of the inhibit string are in a programmed state “00”. In this case, the boosting efficiency is low, and a charge sharing effect among the cells of the inhibit string can disadvantageously induce F-N tunneling in the cells. This is generally referred to as a “program disturbance” effect.
Program disturbance can be reduced by implementing a “local boosting scheme.” Referring to FIG. 6 (where the D cell is to be programmed), the local boosting scheme is executed, for example, by applying a voltage Vlocal (e.g., ˜2V) to one or more word lines preceding the word line receiving the program voltage Vpgm. In the example of FIG. 6, the program voltage is applied to word line WL28, and the voltage Vlocal is applied to the two preceding word lines WL27 and WL26. The remaining word lines receive the voltage Vpass. Program disturbance is reduced by blocking the charge sharing to the adjacent memory cells MC<0:25> of the program inhibited E cell in the inhibit string. However, if the memory cells MC26 and MC27 are in erased states (“11”), local boosting may not sufficiently block the charge sharing path in the inhibit string.
Conventional techniques described above can suffer from over-erasure of memory cells. As shown in FIG. 7, the top figure (a) illustrates a normal distribution of threshold voltages where, as explained earlier, the state “11” is an erase state. The reference character “x1” in the figure denotes the threshold voltage of the program inhibited E cell of FIG. 6 in an erased state. After a program operation (of the F cell) utilizing local boosting, the threshold voltage of the E cell may fall below the normal distribution. This is illustrated by reference character “x2” in the lower diagram (b) of FIG. 7. As a result, subsequent programming of the E cell may result in errors. In an effort to obviate this problem, it is possible to execute pre-program (or post-program) operations in conjunction with each erase routine. However, such operations add significantly to the overall processing time.